1. Technical Field
The present invention relates generally to the field of design automation and computer-aided design (CAD) in the area of development of integrated circuits. More specifically, the present invention provides a system and method for automatic insertion of on-chip decoupling capacitors.
2. Description of Related Art
Complementary Metal Oxide Semiconductor (CMOS) circuit technology of today and its application in synchronously switching digital Very Large Scale Integration (VLSI) systems imposes high frequency current changes on the associated power distribution network formed by power supply wiring and decoupling capacitors. The reason lies in the semiconductor fabrication technology. CMOS circuit technology uses a combination of n- and p-doped semiconductor material to achieve low power dissipation. Any path through a gate through which current can flow includes both n- and p-type transistors. Only one type is turned on in any stable state so there is low static power dissipation. However, a higher current flows when a gate switches in order to charge a parasitic capacitance.
The imposed current changes, in return, generate noise voltages, i.e., unintentional variation of the voltage level. Because of such variations, the supply voltage level might even leave a predetermined voltage range necessary for a faultless operation of the supplied circuits, which jeopardizes the operability of the whole system. Therefore one of the major challenges in modern circuit design is to design a reliable power distribution system, i.e., a power distribution system that provides a voltage supply whose level stays within a predefined range of variation under worst case conditions. Thus, the power distribution network is designed to have a minimum amount of noise voltage even if all gates in the circuit switch at one instant of time.
The general engineering approach is to build up a power distribution network which keeps its impedance as low as possible in each branch from direct current (DC) up to the highest needed frequencies. In such a system power supply, noise is at a minimum. In order to achieve this, the designer designs a suitable power wiring structure and places decoupling capacitors along the power path from the primary power source down to the switching circuits. The decoupling capacitors provide a local capacitance at their placement location. The closer the switching circuit high frequency capacitors are placed, i.e. ones with a good high frequency response, the better the provision for high speed current changes. Ultimately, the power supply decoupling capacitors have to be distributed at the on-chip level itself among the switching circuits.
Traditionally, the distribution of on-chip power supply decoupling capacitors is performed in one of two ways. First, the decoupling capacitors may be defined prior to designing the circuits. That is, the locations and capacitance values are determined prior to the circuit itself being designed. Second, the decoupling capacitors are inserted into the “white space” after the circuit is designed. That is, decoupling capacitors are inserted into locations on the chip where the area permits insertion of decoupling capacitors. Both of these approaches have significant drawbacks in that they do not take into consideration the actual design data to determine the optimum location and capacitance values for decoupling capacitors and do not take into consideration the voltage noise distribution of the integrated circuit.
Therefore, it would be beneficial to have a system and method for automatic insertion of on-chip decoupling capacitors which takes into consideration the design data and predicted noise distribution of the integrated circuit when determining the location and capacitance values of decoupling capacitors.